1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, for reducing current consumption and preserving stored data when a low-power consumption mode is designated.
2. Description of the Related Art
In the technological field of semiconductor memory devices, there is always a demand for low current consumptive devices. A technology has been developed, for example, as described in JP-A-2000-174611, in which a bias voltage is applied to the sources of memory transistors included in a memory cell in order to suppress a current consumption required by the memory device when a low-power consumption mode is designated. The bias voltage to be applied to the sources is presumably set to a rather small value in consideration of a maximum variance in the threshold voltage Vt of the memory transistors so that the data in the memory cell can be preserved.
Since the effect of a bias voltage applied to a substrate is limited, if the threshold voltage Vt is decreased due to a variance caused by high temperature or a manufacturing process, a margin for data preservation becomes excessively large, however, a reduction in a standby current consumption is restricted. In contrast, when the threshold voltage Vt is increased, assuming that the bias voltage to be applied to the sources is set to a rather large value in order to reduce the standby current consumption, the margin for data preservation decreases.
In recent years, the capacity of semiconductor memory devices has increased, and design rules for processes have been contracted. A standby current consumption associated, for example, with a low-power consumption mode tends to pose a problem because of an off-leakage current of a metal-oxide semiconductor (MOS) transistor. Accordingly, there is an increasing demand to suppress the standby current consumption while preserving the data in the memory.